Power semiconductor die are packaged in various leadframe packages that are constructed to handle large currents switched by the dice, and the large amounts of heat generated by the dice. A typical transistor power semiconductor die has a control terminal and a first current-conducting terminal on the “top” surface of the die, and a second current-conducting terminal on the “bottom” surface of the die. The device may be mounted to the leadframe with its top surface facing up, or with its bottom surface facing up. In the former case, the bottom surface of the device is attached to a die attach region of the leadframe, and wire bonds are used to interconnect the terminals at the die's top surface to leads of the leadframe. In the latter case, the terminals at the die's top surface are flip-chip bonded to leads and/or tabs of the leadframe, and a die clip is used to interconnect the terminal at the die's bottom surface to a tab of the leadframe. There is ever increasing demand to increase the amount of power that can be switched by power semiconductor die. However, this would increase the amount of heat generated by the die, and current die packages are limited in the amount of heat they can dissipate without using complex designs. One way to reduce the heat generated by a power semiconductor device is to reduce the length of the electron drift region of the die, which may be done by thinning the device. However, this weakens the die's ability to handle the thermal stresses induced by handling large amounts of power, and often results in the cracking of the die and shorted lifetimes.